Spring 2014 Schedule:

Instructor Dr. Stephen Bruder
  Email: bruders@erau.edu
  Office: KEC 108
  Office hrs: MWF 4-6 pm & T 8-10:30 am
   
TAs Kruszewski, Lauren - kruszewl@my.erau.edu
  McKenna, Jessica - mckennj4@my.erau.edu
  Weidman, Ashley - weidmana@my.erau.edu

Textbook: Fundamentals of Logic Design, 7th Edition by Charles H. Roth and Larry L. Kinney

Course Description:

Introduction to logic design and interfacing digital circuits. Boolean algebra, combinatorial logic circuits,
digital multiplexers, circuit minimization techniques, flip-flop storage elements, shift registers, counting
devices, and sequential logic circuits.

Topics Covered:

  1. Combinational Digital Logic
    • Number systems
    • Binary arithmetic
    • Logic gates
    • Logic operations
    • Arithmetic operations
    • MSI components (Encoders, decoders, MUX, ...)
  2. Sequential Digital Logic
    • Flip-Flops
    • State machines
    • State diagrams
    • Timing
    • Registers, shifters, and counters
    • Basic control unit
  3. Introduction to VHDL
    • A basic introduction to hardware definition languages (specifically VHDL)
    • VHDL design of Combinational & Sequential Circuits

Grading Scructure:

Homework Assignments 20%
Four Mid-Term Exams (12.5% each) 50%
Final Exam 30%

Class Schedule:

Week # Dates Topic Homework Assignments Reading Assignment
1 Mon, Jan 6 -- Winter Break Holiday--    
Wed, Jan 8 Course Introduction (ppt, pdf)

hwk#1, soln#1

 
Fri, Jan 10 Number Systems and Conversions (ppt, pdf) 1.1, 1.2
2 Mon, Jan 13 Binary Arithmetic, Negative Numbers, 2's, and 1's complement (ppt, pdf) 1.3, 1.4
Wed, Jan 15 Binary Codes (ppt, pdf)

hwk#2, soln#2

1.5
Fri, Jan 17 Boolean Algebra (ppt, pdf) 2.1 - 2.5
3 Mon, January 20 -- Martin Luther King Jr. Day Holiday --  
Wed, January 22 Laws of Boolean Algebra (ppt, pdf)

hwk#3, soln3

2.6 - 2.8
Fri, January 24 SOP & POS forms, XOR, & simplification (ppt, pdf) 3.1 - 3.5
4 Mon, January 27 Minterm / Maxterm & Applications of Boolean Algebra (ppt, pdf) 4.1 - 4.4
Wed, January 29 Mid-Term Exam #1

hwk#4, soln4

 
Fri, January 31 Truth Tables, Incomplete Functions, & Full Adder (ppt, pdf) 4.5, 4.6, & 4.7
5 Mon, February 03 Karnaugh Maps (ppt, pdf) 5.1 - 5.3
Wed, February 05 Karnaugh Maps: Four & Five Variables (ppt, pdf)

hwk#5, soln5

5.1 - 5.3
Fri, February 07 Prime Implicants (ppt, pdf) 5.4
6 Mon, February 10 Multi-Level Gate Circuit (ppt, pdf) 7.1 - 7.3
Wed, February 12 NAND/NOR Multi-Level Gate Circuits (ppt, pdf)

hwk#6, soln6

7.4 - 7.7
Fri, February 14 Timing diagrams, Multiplexers & Tri-State Buffers (ppt, pdf) 8.3, 8.4, 9.1 - 9.3
7 Mon, February 17 -- Presidents Day Holiday --  
Wed, February 19 Decoders, Encoders, and Read-Only Memories (ppt, pdf)

hwk#7,soln7

9.4, 9.5
Fri, February 21 Programmable Logic Devices (ppt, pdf) 9.6, 9.8
8 Mon, February 24 Introduction to VHDL (ppt, pdf) 10.1 - 10.3
Wed, February 26 More on VHDL (ppt, pdf) VHDL_code   10.4 - 10.9
Fri, February 28 Mid-Term Exam #2  
9 Mon, March 03

Review of Mid-Term Exam #2

 
Wed, March 05

Latches (ppt, pdf) VHDL_code

hwk#8, soln#8

11.1 - 11.4
Fri, March 07 Flip-Flops (ppt, pdf) VHDL Code 11.6 - 11.10
10 Mon, March 10 -- Spring Break --  
Wed, March 12 -- Spring Break --  
Fri, March 14 -- Spring Break --  
11 Mon, March 17 Shift Regs, Counters, State (transition) Graphs (ppt, pdf) 12.1 - 12.3
Wed, March 19 VHDL in sequential logic (ppt, pdf) VHDL_code

hwk#9, soln#9

17.1 - 17.3
Fri, March 21 Sequential Circuits & Counter design (ppt, pdf) 12.3 - 12.4
12 Mon, March 24 Counters using S-R and J-K FFs (ppt, pdf) 12.5 - 12.6
Wed, March 26 Mid-Term Exam #3

hwk#10, soln#10

 
Fri, March 28 Mealy and Moore State Machines (ppt, pdf) 13.1, 13.4
13 Mon, March 31

Timing Diagrams (ppt, pdf) VHDL_code

13.2, 13.3
Wed, April 02 Review of Mid-Term Exam #3 hwk#11, soln#11  
Fri, April 04 Sequence Detector design (ppt, pdf) 14.2, 14.3, 14.5, & 14.6
14 Mon, April 07 State Reduction (ppt, pdf) 15.1 - 15.3
Wed, April 09 State Assignments (ppt, pdf)

hwk#12, soln#12

VHDL code

15.7 - 15.9
Fri, April 11 State Machine Design with SM Charts (ppt, pdf) 19.1 - 19.3
15 Mon, April 14 Dice Game design (ppt, pdf)  
Wed, April 16

Sequential Circuit Design Using PLA, CPLD, and FPGA devices (ppt, pdf)

  16.4 - 16.6
Fri, April 18 Mid-Term Exam #4  
16 Mon, April 21 Intro to Computer architecture (ppt, pdf)  
Wed, April 23 Course Review / Mid4 Review (ppt, pdf)    
Fri, April 25 Study day    
17

Mon, April 28: 5 to 7 pm in the DLC Auditorium

Final Exam

in the DLC Auditorium