Spring 2015 Schedule:

Textbook: Fundamentals of Logic Design, 7th Edition by Charles H. Roth and Larry L. Kinney

Course Description:

Introduction to logic design and interfacing digital circuits. Boolean algebra, combinatorial logic circuits,
digital multiplexers, circuit minimization techniques, flip-flop storage elements, shift registers, counting
devices, and sequential logic circuits.

Topics Covered:

Instructor Dr. Stephen Bruder
  Email: bruders@erau.edu
  Office: KEC 108
  Office hrs: MWF 10:30 - 11:30am, 1 - 2pm, and Thur 7:30-9:30am
  Help Session: Monday 5 - 6 pm in KEC 126
   
TAs Kruszewski, Lauren - kruszewl@my.erau.edu
  Randolph, Dalton: randold1@my.erau.edu
  1. Combinational Digital Logic
    • Number systems
    • Binary arithmetic
    • Logic gates
    • Logic operations
    • Arithmetic operations
    • MSI components (Encoders, decoders, MUX, ...)
  2. Sequential Digital Logic
    • Flip-Flops
    • State machines
    • State diagrams
    • Timing
    • Registers, shifters, and counters
    • Basic control unit
  3. Introduction to VHDL
    • A basic introduction to hardware definition languages (specifically VHDL)
    • VHDL design of Combinational & Sequential Circuits

Grading Structure:

Homework Assignments 25%
Three Mid-Term Exams (15% each) 45%
Final Exam 30%

Class Schedule:

Week # Dates Topic Homework Assignments Reading Assignment
1        
Wed, Jan 7 Course Introduction (ppt, pdf)

hwk#1, soln#1

 
Fri, Jan 9 Number Systems and Conversions (ppt, pdf) 1.1, 1.2
2 Mon, Jan 12 Binary Arithmetic, Negative Numbers, 2's, and 1's complement (ppt, pdf) 1.3, 1.4
Wed, Jan 14 Binary Codes (ppt, pdf)

hwk#2, soln#2

1.5
Fri, Jan 16 Boolean Algebra (ppt, pdf) 2.1 - 2.5
3 Mon, January 19 Martin Luther King Jr. Day Holiday  
Wed, January 21 Laws of Boolean Algebra (ppt, pdf)

hwk#3, soln3

2.6 - 2.8
Fri, January 23 SOP & POS forms, XOR, & simplification (ppt, pdf) 3.1 - 3.5
4 Mon, January 26 Minterm / Maxterm & Applications of Boolean Algebra (ppt, pdf) 4.1 - 4.4
Wed, January 28 Truth Tables, Incomplete Functions, & Full Adder (ppt, pdf)

hwk#4, soln4

4.5, 4.6, & 4.7
Fri, January 30 Karnaugh Maps (ppt, pdf) 5.1 - 5.3
5 Mon, February 02 Karnaugh Maps: Four & Five Variables (ppt, pdf) 5.1 - 5.3
Wed, February 04 Prime Implicants (ppt, pdf)

hwk#5, soln5

5.4
Fri, February 06
Mid-Term Exam #1
 
6 Mon, February 9 Review of Mid-Term Exam #1  
Wed, February 11 Multi-Level Gate Circuit (ppt, pdf)

hwk#6, soln6

7.1 - 7.3
Fri, February 13 NAND/NOR Multi-Level Gate Circuits (ppt, pdf) 7.4 - 7.7
7 Mon, February 16 Presidents Day Holiday  
Wed, February 18 Timing diagrams, Multiplexers & Tri-State Buffers (ppt, pdf)

hwk#7,soln7

8.3, 8.4, 9.1 - 9.3
Fri, February 20 Decoders, Encoders, and Read-Only Memories (ppt, pdf) 9.4, 9.5
8 Mon, February 23 Programmable Logic Devices (ppt, pdf) 9.6, 9.8
Wed, February 25 Introduction to VHDL (ppt, pdf) hwk#8, soln#8 10.1 - 10.3
Fri, February 27 More on VHDL (ppt, pdf) VHDL_code 10.4 - 10.9
9 Mon, March 02

Latches (ppt, pdf) VHDL_code

11.1 - 11.4
Wed, March 04 Flip-Flops (ppt, pdf) VHDL Code

 

11.6 - 11.10
Fri, March 06
Mid-Term Exam #2
 
10 Mon, March 9 -- Spring Break --  
Wed, March 11 -- Spring Break --  
Fri, March 13 -- Spring Break --  
11 Mon, March 16 Review of Mid-Term Exam #2  
Wed, March 18 Shift Regs, Counters, State (transition) Graphs (ppt, pdf)

hwk#9, soln#9

12.1 - 12.3
Fri, March 20 Sequential Circuits & Counter design (ppt, pdf) 17.1 - 17.3
12 Mon, March 23 Counters using S-R and J-K FFs (ppt, pdf) 12.3 - 12.4
Wed, March 25 VHDL in sequential logic (ppt, pdf) VHDL_code

hwk#10, soln#10

12.5 - 12.6
Fri, March 27 Mealy and Moore State Machines (ppt, pdf) 13.1, 13.4
13 Mon, March 30

Timing Diagrams (ppt, pdf) VHDL_code

13.2, 13.3
Wed, April 01 Sequence Detector design (ppt, pdf) hwk#11, soln#11  
Fri, April 03 More FSM Examples (ppt, pdf) 14.2, 14.3, 14.5, & 14.6
14 Mon, April 06 Dice Game design (ppt, pdf)  
Wed, April 08 State Reduction (ppt, pdf)

hwk#12, soln#12

15.1 - 15.3
Fri, April 10 State Assignments (ppt, pdf) 15.7 - 15.9
15 Mon, April 13 Re-Visit Dice Game (ppt, pdf) 19.1 - 19.3
Wed, April 15

State Machine Design with SM Charts (ppt, pdf)

   
Fri, April 17 Mid-Term Exam #3  
16 Mon, April 20 Review of Mid-Term Exam #3  
Wed, April 22 Course Review    
Fri, April 24 Study day    
17

Monday, April 27
2:45 to 4:45 p.m.

Common Final Exam
(in KEC Room 126 )

   

Academic Integrity/Conduct:

Embry-Riddle is committed to maintaining and upholding intellectual integrity. All students, faculty, and staff have obligations to prevent violations of academic integrity and take corrective action when they occur. The adjudication process will include the sanction imposed on students who commit the following academic violations, which may include a failing grade on the assignment, a failing grade for the course, suspension, or dismissal from the University.

  1. Plagiarism: Presenting as one’s own the ideas, words, or products of another. Plagiarism includes use of any source to complete academic assignments without proper acknowledgment of the source.
  2. Cheating is a broad term that includes the following:
    1. Giving or receiving help from unauthorized persons or materials during examinations.
    2. The unauthorized communication of examination questions prior to, during, or following administration of the examination.
    3. Collaboration on examinations or assignments expected to be individual work.
    4. Fraud and deceit, which include knowingly furnishing false or misleading information or failing to furnish appropriate information when requested, such as when applying for admission to the University.

Access To Learning:

ERAU is committed to the success of all students. It is University policy to provide reasonable accommodations to students with disabilities who qualify for services. If you would like to discuss and/or request accommodations, please contact Disability Support Services in Building 17, extension 6750, or 928/777-6750.

Continuity Statement:

In the event of a temporary campus closure this course will continue on Blackboard with ongoing communications to occur through electronic means.  Assignments are provided in the syllabus and should be completed in a timely manner.  Further instructions will be posted on Blackboard regarding testing and submission of work.