2015 Spring Schedule:

Instructor Dr. Stephen Bruder
  Email: bruders@erau.edu
  Office: KEC 108
  Office hrs: MWF 10:30 - 11:30am, 1 - 2pm, and Thur 7:30-9:30am
TAs Thacker, Blake: thackeb1@my.erau.edu
  Randolph, Dalton: randold1@my.erau.edu

Textbook: None

Course Description:

Laboratory experiments in the measurement and verification of digital circuits. Discrete and integrated logic circuit design analysis and measurements.

Course Objectives:

Required Equipment:

  1. A Digilent BASYS 2 Spartan-3EFPGA board (~$69)
  2. A Digilent Analog Discovery oscilloscope/logic analyzer/signal generator/... (~$99)
  3. A small bin of parts (~$30)


Grading for each of the Labs (Lab 11 is counted twice):
  Points Percent of Grade
Pre-Lab 20 points 10 %
Lab Report 180 points each 90 %
BONUS Question 20 points each 10 %
TOTAL 220 points 110 %

Lab Schedule:

Dates Lab Description
Thur, Jan 15 Lab 0: Organizational Meeting (Attendance required)
Thur, Jan 22 Lab 1: Introduction to Digital Lab (Lab_1.bit file)
Thur, Jan 29 Lab 2: Logic Levels and Logic Gates (Lab2_Experiment3.zip and Lab2_Experiment2.bit file)
Thur, Feb 05 Lab 3: Basic Combinational Logic Circuits
Thur, Feb 12 Lab 4: Arithmetic Logic Circuits (adder.ucf)
Thur, Feb 19 Lab 5: Multi-Input / Multi-Output Logic (Lab_05.zip)
Thur, Feb 26 Lab 6: Multiplexers and Encoders
Thur, March 05 Lab 7: Introduction to a Hardware Definition Language (VHDL) (VDHL files)
week 10 Spring Break
Thur, March 19 Lab 8: Debouncing a SPDT Switch
Thur, March 26 Lab 9: Lab 9: Design of Counters (VHDL code)
Thur, April 02 Lab 10: Driving a Servo-Motor with PWM - FORMAL LAB REPORT REQUIRED
VHDL Code to display desired angle on 7-Segment Display (disp_on_7_seg.vhd, lab_10.ucf)
Thur, April 09 Lab 11: A dice Game (Craps) - FORMAL LAB REPORT REQUIRED
VHDL Code to display up to four BCD numbers (disp_dice.vhd) -- Different from Lab 10 code!!
Thur, April 16 Lab 11: A dice Game (Craps) - FORMAL LAB REPORT REQUIRED

Academic Integrity/Conduct:

Embry-Riddle is committed to maintaining and upholding intellectual integrity. All students, faculty, and staff have obligations to prevent violations of academic integrity and take corrective action when they occur. The adjudication process will include the sanction imposed on students who commit the following academic violations, which may include a failing grade on the assignment, a failing grade for the course, suspension, or dismissal from the University.

  1. Plagiarism: Presenting as one’s own the ideas, words, or products of another. Plagiarism includes use of any source to complete academic assignments without proper acknowledgment of the source.
  2. Cheating is a broad term that includes the following:
    • Giving or receiving help from unauthorized persons or materials during examinations.
    • The unauthorized communication of examination questions prior to, during, or following administration of the examination.
    • Collaboration on examinations or assignments expected to be individual work.
Fraud and deceit, which include knowingly furnishing false or misleading information or failing to furnish appropriate information when requested, such as when applying for admission to the University.

Reference Material:

Software Required to Work from Home:

  1. ADEPT Download - The free Digilent ADEPT software is required to connect to your FPGA board.
  2. WAVEFORMS Download- The free Digilent WAVEFORMS program is required to operate your Analog Discovery.
  3. Xilinx ISE Design Suite (WebPack) - see below for details

Component Datasheets:

Basys2 FPGA Board:

Getting Started Videos (courtesy of Blake Thacker - ERAU):

  1. Creating your first schematic in ISE
  2. ????

Analog Discovery Videos (courtesy of Digilent):

  1. Analog Discovery Quickstart #1: Getting Started
  2. Analog Discovery Quickstart #2: Power Supply Tool
  3. Analog Discovery Quickstart #3: Voltmeter Tool
  4. Analog Discovery Quickstart #4: Arbitrary Waveform Generator
  5. Analog Discovery Quickstart #5: The Oscilloscope
  6. Additional Information/Projects (includes excellent videos)

Analog Discovery Connections (pdf file):


Xilinx ISE Design Suite (we have the WebPack):